conditional operator (?:) vs IF statement

Here is the simple code for comparing conditional operator and if statement.

Code:

module testing;

  reg foo;

  wire [3:0] c1,c2,c3;

  reg [3:0] a=1,b=3,cif1,cif2,cif3;

  

  assign c1 = foo ? a : b;  

  //equality
  assign c2 = (foo==1) ? a : b;

  //case equality
  assign c3 = (foo===1) ? a : b;

  

  always@(foo or a or b) begin 

    if (foo) 

      cif1 = a;

    else 

      cif1 = b;

    //equality

    if (foo==1) 

      cif2 = a;

    else 

      cif2 = b;

    //case equality

    if (foo===1) 

      cif3 = a;

    else 

      cif3 = b;

  end

  

  initial begin

    $monitor("@%3t :: foo=%b, a=%x, b=%x,   c1=%x, c2=%x, c3=%x,   cif1=%x ,cif2=%x ,cif3=%x", $realtime,foo,a,b,c1,c2,c3,cif1,cif2,cif3);

    #10 foo=1;

      #5 a=a+1;

    #10 foo=0;

      #5 b=b+1;

    #10 foo=1;

  end

  

endmodule

OUTPUT:

@  0 :: foo=x, a=1, b=3,   c1=X, c2=X, c3=3,   cif1=3 ,cif2=3 ,cif3=3  @ 10 :: foo=1, a=1, b=3,   c1=1, c2=1, c3=1,   cif1=1 ,cif2=1 ,cif3=1  @ 15 :: foo=1, a=2, b=3,   c1=2, c2=2, c3=2,   cif1=2 ,cif2=2 ,cif3=2  @ 25 :: foo=0, a=2, b=3,   c1=3, c2=3, c3=3,   cif1=3 ,cif2=3 ,cif3=3  @ 30 :: foo=0, a=2, b=4,   c1=4, c2=4, c3=4,   cif1=4 ,cif2=4 ,cif3=4  @ 40 :: foo=1, a=2, b=4,   c1=2, c2=2, c3=2,   cif1=2 ,cif2=2 ,cif3=2  

Based on the simulation, when the condition is X conditional operator outputs X whereas if statement outputs else part. Except this, moreover no difference in execution of these two.

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Hardware/Software cosimulation using Xilinx and Matlab

Technology has advanced, meanwhile software has become powerful.  Xilinx & Matlab has worked together to bring hardware cosimulation, where some part of the code will be executing from Xilinx FPGA and input/output can be from Matlab. This is useful for audio, image and signal processing.

This video series describes the Hardware/Software cosimulation of verilog and VHDL coding inside FPGA using Xilinx and Matlab.

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Useful SED commands - Linux SED

    While working in Linux, SED always plays important role in text processing. Here we've given some common examples of SED usage. Hope it will be a life saving that comes in handy!!!!!

  Let us know your shortcuts/ commands in comment section below that saved your time...

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VERILOG TIMESCALE - TIMEFORMAT - EXAMPLE

In this post, let us see the timescale feature and system tasks that are available in Verilog HDL with brief examples.

`timescale directive specifies the time unit and time precision of the modules that follow it. The time unit is the unit of measurement for time values such as the simulation time and delay values.

Syntax:   `timescale <time_unit>/<time_precision>

              The time_unit argument specifies the unit of measurement for times and delays.

The time_precision argument specifies how delay values are rounded before being used in simulation. The smallest time_precision argument of all the 'timescale compiler directives in the design determines the precision of the time unit of the simulation.

The time_precision argument shall be at least as precise as the time_unit argument; it cannot specify a longer unit of time than time_unit. The integers in these arguments specify an order of magnitude for the size of the value; the valid integers are 1, 10, and 100. The character strings "s, ms, us, ns, ps, and fs " represent units of measurement;

Example: `timescale 1ns/100ps

                Here in the above example, time_unit is 1ns & time_precision is 100ps. So the delay of #1 in the code is equivalent to 1ns delay in simulation. The delay of #1.56 will be rounded to 1.6ns. i.e. the decimal fraction will be rounded to in multiples of the time_precision value. Each #delay value is rounded to time delays w.r.t the timescale specified and added to the current simulation time.

Some of the system tasks on timescale are

·         $printtimescale() prints the timescale settings of the current scope of the file.

·         $timeformat(..,..,,,) system task

The $timeformat system task performs the following two operations:

Ø  It sets the time unit for all later-entered delays entered interactively.

Ø  It sets the time unit, precision number, suffix string, and minimum field width for all %t formats specified in all modules that follow in the source description until another $timeformat system task is invoked.

Syntax for $timeformat is

$timeformat ( units_number , precision_number , suffix_string , minimum_field_width ) ;

Example: $timeformat(-9,3,"ns",8);   This will display any %t string in ns with 3 digits precision, and 8 characters string size.

Let us see the code for the example used for different timescale settings & $timeformat system task.

initial begin

    $timeformat(-9,3,"ns",8);

    #1     $display("\n1) %t",$realtime); 

    #10.5  $display("\n2) %t",$realtime); 

    #10.56 $display("\n3) %t",$realtime);

    #10.56 $display("\n4) %t",$realtime);

    #11.46 $display("\n5) %t",$realtime);

 $finish;

end

The output of the above code with different timescale values are illustrated in the below table.

Timescale	`timescale 1ns/1ps	`timescale 1ns/10ps	`timescale 1ns/100ps
Output	1)  1.000ns 2) 11.500ns 3) 22.060ns 4) 32.620ns 5) 44.080ns	1)  1.000ns 2) 11.500ns 3) 22.060ns 4) 32.620ns 5) 44.080ns	1)  1.000ns 2) 11.500ns 3) 22.100ns 4) 32.700ns 5) 44.200ns

The calculation for timescale 1ns/100ps is as below:

1.       Step 1, time is 1ns

2.       Step 2, time is (1ns+10.5ns)=11.5ns

3.       Step 3, time is (11.5ns + 10.6ns) = 22.1ns

4.       Step 4, time is (22.1ns + 10.6ns) = 32.7ns

5.       Step 5, time is (32.7ns + 11.5ns) = 44.2ns

 Similarly you could calculate for different timescale values. If you've any queries, plz do comment it.

If you enjoyed this post plz let us know your views via comments.
This helps us to do much more better.
Thankyou.

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Perl – File Read Write Example

Perl – File Read Write Example

In this post, let’s see how to remove the new line character or line break in a text file and save the result in another text file.

Refer to other posts File handling, RegEx.

To accomplish the removal of new line character, we use RegEx substitution operator. The code for substitution is as below,

    $a =~ s/\n//;   # $a is the variable in which the replacement takes place

·         The input to the script is through command line arguments. The command line inputs are stored in the array variable @ARGV (please note the CAPS). First we check the size. If no command line arguments is specified, the size of ARGV is -1. If so, the script prints the usage & exits, using the in-built function die().

unless($#ARGV <0) {

    $in_file=$ARGV[0];

} else {

    die "\nUsage:\n remove_new_line.pl <input_file>\n";

}

·         If valid input is provided, then open the specified file in read mode as below. If unable to open the file, exit with a note printed.  $! Is the Perl system variable which prints the error from the OS.

  open FIN, "<$in_file" or die "Unable to read '$in_file' :$!";

·         Create the output file by appending the name “new_” to the input file name.

open FOUT, ">new_$in_file" or die "Unable to create 'new_$in_file' :$!";

·         Then create a loop, that executes for each line of the input file. Then remove the newline character and write back the result to output file.

while ($a=<FIN>) {

  # remove \n character

    $a =~ s/\n//;

  # write the new data to text file

    print FOUT $a;

 }

Sample output of this script:

            Top file is the input & bottom file is the output.

Click here to download this script.

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   A regular expression or RegEx is a string of characters that define the pattern or patterns you are viewing. The syntax of regular expressions in Perl is very similar to what you will find within other regular expression, supporting programs, such as sed, grep, and awk. 

   In this post, Perl regex is illustrated with examples.

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Glitch Free Clock Gating - verilog good clock gating

   Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. This saves power by adding more logic to a circuit to the clock by disabling clock switching, so that the flip-flops in them do not have to switch states. As a result, the switching power consumption goes to zero, and only leakage currents are incurred.

   Clock gating logic can be added into a design in a variety of ways:

1. Coded into the RTL code as enable conditions that can be automatically translated into clock gating logic by synthesis tools.
   
2. Inserted into the design manually by the RTL designers (typically as module level clock gating) by instantiating library specific ICG (Integrated Clock Gating) cells to gate the clocks of specific modules or registers.
   
3. Semi-automatically inserted into the RTL by automated clock gating tools. These tools either insert ICG cells into the RTL, or add enable conditions into the RTL code. These typically also offer sequential clock gating optimisations.

   Poor clock gating produces glitches in the output clock, making unwanted clock transitions which may lead to timing violations,etc., and increased power consumption.

   Here is an Verilog example illustrating the RTL code for clock gating & its issues.

The below code produces simple clock gating mechanism with an 2-input AND gate, with inputs as CLK & CLK_EN. But the greatest disadvantage is that it produces glitches in output as in the below waveform.

//BAD clock gating, can cause glitches in output
 assign clk_out1 = c_en && clk;

To overcome the glitches, a latching needs to be added to change the enable only when CLK is high/low. By this way, glitches are avoided & produces a good clock for the rest of the block. 

//GOOD clock gating & glitch free
 always @ (c_en or clk) begin
     if (!clk)
        en_out2 = c_en; // build latch
 end
 assign clk_out2 = en_out2 && clk;

Circuit synthesized for the above codes:

Verilog RTL - Clock gating- circuit :: ELecDude

Waveform for the above code:

Click here for better view of waveform.

If you enjoyed this post plz let us know your views via comments.
This helps us to do much more better.
Thankyou.

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Download Verilog codes for SPI Master and Slave modules

Sharing below the links for SPI Verilog codes for Master and Slave modules.

SPI means Serial Pheripheral Interface, is a synchronous serial data link operating in full duplex mode.

For detailed information of the Verilog code of SPI Master and Slaves modules, proceed to the below links.

• SPI MASTER SLAVE Verilog Code - SPI Working Modes of Operation - Applications - Advantages Disadvantages   
• SPI Verilog code - Master Slave code with testbench

 For Verilog code of SPI Master and Slaves modules code download & discussions, click here.

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PERL TUTORIAL PART 4 - Working with files

FILE HANDLING

     The basics of handling files are simple, just associate a filehandle with an external file and then use a variety of operators and functions within Perl to read and update the data stored within the data stream associated with the filehandle. The filehandle is the name for an I/O connection between the Perl process and the outside world.

     A filehandle is a named internal Perl structure that associates a physical file with a name. The mode of operation must be specified for the filehandle is opened.

     Three basic file handles are - STDIN, STDOUT, and STDERR which represent standard input, standard output and standard error devices respectively. Apart from these, any number of filehandles can be added in the code.

The different file operations are:

1) Opening a file

2) Closing the file

3) File Reading

4) File Writing

5) File tests

1) Opening a file

The syntax for opening a file is as follows:

open(FILEHANDLE,"<mode>file_name");

or simply

open(FILEHANDLE,"mode","file_name");

where mode specifies the type of file access.

MODE SYMBOL	ACCESS TYPE
< or r	Read Only Access
> or w	Creates, Writes, and Truncates
>> or a	Writes, Appends, and Creates
+< or r+	Reads and Writes
+> or w+	Reads, Writes, Creates, and Truncates
+>> or a+	Reads, Writes, Appends, and Creates

Most commonly used are <, >, >>.

It is a good practice to use capital letters for filehandles. And for safe operation, it is always recommended to use the DIE(....) function for file open which will terminate the program when it fails to open the file.

open(FILEHANDLE,"mode","file_name") or die "Unable to open the file(file_name)";

Example:

open(FH1R,"<","file1.txt") or die "Unable to open the file(file1.txt) in read mode!";

open(FH2W,">file2.txt") || die "Unable to open the file(file2.txt) to write!";

$logfilename="log.txt"

open(LOG,">>",$logfilename) || die "Unable to open the file(log.txt) in append mode!!!";

2) Closing the file

To close a file simply call the CLOSE(...) function with the filehandle as input. All the filehanldes are automatically closed when the Perl program terminates. The syntax is

close(FILEHANDLE);

3) Reading from a file

To read the contents from the file, <> operator is used, just like STDIN.

Example:

$line_1=<FH1R>; #reads only one line

@lines=<FH1R>; #reads the entire file, & places in the array

4) Writing to a file

Writing data to a file is simply like printing to STDOUT, except the filehandle is used between the print keyword & data.

Example:

print FH2W "Hello!! This is 1st line...\n";

5) File testing

File tests are performed on file handles to determine the file properties. For example –e FileHandle returns true if the file pointed by FileHandle exists in the system. The below table shows the different file test that can be performed in Perl. Note that the CAPITAL and small letter tests produces different results.

PARAMETER	DESCRIPTION
-r	File or directory is readable
-w	File or directory is writable
-x	File or directory is executable
-o	File or directory is owned by user
-R	File or directory is readable by real user, not effective user (differs from -r for setuid programs)
-W	File or directory is writable by real user, not effective user (differs from -w for setuid programs)
-X	File or directory is executable by real user, not effective user (differs from -x for setuid programs)
-O	File or directory is owned by real user, not effective user (differs from -o for setuid programs)
-e	File or directory exists
-z	File exists and has zero size (directories are never empty)
-s	File or directory exists and has nonzero size (the value is the size in bytes)
-f	Entry is a plain file
-d	Entry is a directory
-S	Entry is a socket
-p	Entry is a named pipe (a "fifo")
-t	isatty() on the filehandle is true
-T	File is "text"
-B	File is "binary"
-c	Entry is a character-special file
-M	Modification age in days
-A	Access age in days
-C	Inode -modification age in days

Example:

if (-e FH1)

print "File FH1 exists\n";

if (-T FH1)

print "File FH1 exists & is a Text file\n";

$size= -s FH1;

print "File size is $size bytes...\n";

Click here to download the example code for file handling...


Click the below links to read other tutorials:

• Perl - Basics
• Perl - Operators & STD input output
• Perl - Control structures & loops 

We welcome your valuable comments and suggestion.

It helps us to do better in future.

Thank you.

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