PWM USING AVR ATMEGA8 - TUTORIAL - HEADER

PWM WAVE GENERATION USING AVR ATMEGA8

         This uses AVR aTMega8 Atmel RISC controller ATMEGA8 & generates a PWM wave generation using its on-chip pheripheral by controlling the TCCR1 registers.


         Pulse-width modulation (PWM), or pulse-duration modulation (PDM), is a commonly used technique for controlling power to inertial electrical devices, made practical by modern electronic power switches.

        The average value of voltage (and current) fed to the load is controlled by turning the switch between supply and load on and off at a fast pace. The longer the switch is on compared to the off periods, the higher the power supplied to the load is.

        The term duty cycle describes the proportion of 'on' time to the regular interval or 'period' of time; a low duty cycle corresponds to low power, because the power is off for most of the time. Duty cycle is expressed in percent, 100% being fully on.

       The main advantage of PWM is that power loss in the switching devices is very low. When a switch is off there is practically no current, and when it is on, there is almost no voltage drop across the switch. Power loss, being the product of voltage and current, is thus in both cases close to zero. PWM also works well with digital controls, which, because of their on/off nature, can easily set the needed duty cycle.

PWM in AVR ATMEGA8:

     This project is a simple  PWM program that increases/decreases width 20% when switch SW1/SW2 is pressed. The current pulse duration is displayed in the LCD module.  

       The PWM output is taken through OC1A & OC1B pins of ATmega 8 MCU.  The PWM mode is fast pwm WGM=6, non-inv mode.

Code: 

#define F_CPU 1000000UL

//Fclkio=2MHz for FCPU=2MHz

#include <avr/io.h>

#include <avr/interrupt.h>

#include <util/delay.h>

/*****************MACRO's DEFINITION*********************************/

#define BIT(x)            (1 << (x))  //Set a particular bit mask

#define CHECKBIT(x,b)        (x & BIT(b))        //Checks bit status

#define SETBIT(x,b)    x|=BIT(b); //Sets the particular bit

#define CLEARBIT(x,b)         x&=~BIT(b);      //Sets the particular bit

#define TOGGLEBIT(x,b)      x^=BIT(b); //Toggles the particular bit

#include "lcd.h"

void WaitMs(unsigned int ms);

#define PRT PIND

#define sw1 0

#define sw2 1

#define sw3 2

#define sw4 3

#define TIME 150

unsigned int button(unsigned char PIN);

unsigned int width_us = 204,w=200;             //Default Pulse width in us.

void set_PWM(void);

int main()

{

    unsigned int step=101;//19% of 512

    DDRD=0xC0; PORTD=0xFF;//enable PD as i/p & enable pull-ups

//fast pwm WGM=6, non-inv mode

    TCCR1A=0xA2;

    TCCR1B=(1<<WGM12);

       

    SETBIT(DDRB,1)//set OC1A as o/p

    CLEARBIT(PORTB,1)//clear PB1/OC1A

    SETBIT(DDRB,2)//set OC1B as o/p

    CLEARBIT(PORTB,2)//clear PB1/OC1B

    LCDInit(BBLINK);

    WaitMs(200);

    LCDWriteStringXY(0,0,"Switch= *");

    LCDWriteStringXY(0,1," Width=    us");

    set_PWM();

    SETBIT(TCCR1B,CS10)//start tim1 @ Fclkio

 while(1)

        {

            TOGGLEBIT(PORTD,7)

            if(button(sw1))   //If SW1 is pressed then..

             {

               width_us += step;              //Set pulse width to 2ms

               LCDShowValueXY(8,0,1);

               set_PWM();                       

               WaitMs(1000);

             }

            if(button(sw2))   //If SW2 is pressed then..

             {

               width_us -= step;               //Set pulse width to 1.5ms

               LCDShowValueXY(8,0,2);

               set_PWM();                       

                  WaitMs(1000);

              }

            if(CHECKBIT(TIFR,TOV1)==1)       TOGGLEBIT(PORTD,6)

        }

 return 0;

}

/* waits (pauses) for ms milliseconds */

void WaitMs(unsigned int ms)

{

        unsigned int m;

        for(m=0;m<=ms/10;m++)

        {

                _delay_ms(10);

        }

}

void set_PWM(void)                     //Load appropriate value onto OCR1A & OCR1B Register according to option chosen.

{

        OCR1B = w;

        w=(width_us &0x01FF);

        LCDWriteIntXY(8,1,w,3);

        OCR1A = w;

}

/********    SWITCHES   *******/

unsigned int button(unsigned char PIN)

{

        if(CHECKBIT(PRT,PIN) == 0)

        {

                WaitMs(TIME);

                if(CHECKBIT(PRT,PIN) == 0)

                {

                        return 1;

                }

                else

                        return 0;

        }

        return 0;

}

• CLICK HERE TO DOWNLOAD C file (main program file)

Proteus output demo:

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PROTEUS DESIGN SUITE 7.0 - DOWNLOAD - EXAMPLES

      The Proteus Design Suite is wholly unique in offering the ability to co-simulate both high and low-level micro-controller code in the context of a mixed-mode SPICE circuit simulation. With this Virtual System Modelling facility, you can transform your product design cycle, reaping huge rewards in terms of reduced time to market and lower costs of development.

        Proteus VSM was the first product to bridge the gap between schematic and PCB for embedded design, offering system level simulation of microcontroller based designs inside the schematic package itself.

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          Keil development tools for the 8051 Microcontroller Architecture support every level of software developer from the professional applications engineer to the student just learning about embedded software development.

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UNIVERSAL SHIFT REG VHDL CODE

UNIVERSAL SHIFT REG

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity reg is

port(din:in STD_LOGIC_VECTOR(3 downto 0);

clk,rst: in std_logic;

S:in STD_LOGIC_vector(1 downto 0);

dout:inout std_logic_vector(3 downto 0));

end reg;

architecture Behavioral of reg is

signal msbin,lsbin:STD_LOGIC;

begin

process(clk,rst)

begin

if(rst='1') then

dout <= "0000";

elsif(clk'event and clk='1') then

msbin <= din(3);

lsbin <= din(0);

case S is

when "00" => dout <= dout;--hold

when "01" => dout <= msbin & dout(3 downto 1);-- right shift

when "10" => dout <= dout(2 downto 0) & lsbin;-- left shift

when "11" => dout <= din;-- parallel

when others => dout <= "XXXX";

end case;

end if;

end process;

end Behavioral;

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RAM VLSI CODE

//RAM

module ram( we, en, addr, di, dout);

input        we;

input        en;

input  [4:0] addr;

input  [3:0] di;

output [3:0] dout;

reg    [3:0] RAM [31:0];

reg    [3:0] dout;

always @(en)

                begin

                   if (en) begin

                      if (we)

                                 RAM[addr] <= di;

                      else

                                 dout <= RAM[addr];

                   end

                end

endmodule

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TRAFFIC LIGHT CONTROLLER VLSI CODE

//TRAFFIC LIGHT CONTROLLER

module tlc(N,E,W,S,clk);

output [2:0] N,E,W,S;

input clk;

parameter s0=3'b000;

parameter s1=3'b001;

parameter s2=3'b010;

parameter s3=3'b011;

parameter s4=3'b100;

parameter s5=3'b101;

parameter s6=3'b110;

parameter s7=3'b111;

parameter R=3'b001;

parameter Y=3'b010;

parameter G=3'b100;

reg [2:0] N,E,W,S;

reg [2:0] state;

integer t=0;

initial    //initialize

 begin

      state <= s0;

      t <= 0;

 end

//--------------TIMING CONTROL-----------

always@(posedge clk)

 begin

//  next_state=state;

  case(state)

   s0:if(t==20) //N=G

         begin

            state=s1;

              t=0;

         end

      else

         t=t+1;

   s1:if(t==5)       //N=Y

         begin

            state=s2;

              t=0;

         end

      else

         t=t+1;

     s2:if(t==20)    //E=G

         begin

            state=s3;

              t=0;

         end

      else

         t=t+1;

   s3:if(t==5)       //E=Y

         begin

            state=s4;

              t=0;

         end

      else

         t=t+1;

               

     s4:if(t==20)    //S=G

         begin

            state=s5;

              t=0;

         end

      else

         t=t+1;

   s5:if(t==5)       //S=Y

         begin

            state=s6;

              t=0;

         end

      else

         t=t+1;

               

     s6:if(t==20)    //W=G

         begin

            state=s7;

              t=0;

         end

      else

         t=t+1;

   s7:if(t==5)       //W=Y

         begin

            state=s0;

              t=0;

         end

      else

         t=t+1;

   default: state=s0;

  endcase

 end  //end of always block

//--------------LIGHT CONTROL-----------

 always @ (state)

  begin

      case (state)

         s0:{N,E,W,S}={G,R,R,R};

            s1:{N,E,W,S}={Y,R,R,R};

            

            s2:{N,E,W,S}={R,G,R,R};

            s3:{N,E,W,S}={R,Y,R,R};

          

            s4:{N,E,W,S}={R,R,G,R};

            s5:{N,E,W,S}={R,R,Y,R};

           

            s6:{N,E,W,S}={R,R,R,G};

            s7:{N,E,W,S}={R,R,R,Y};

            default:{N,E,W,S}={G,R,R,R};

      endcase

  end

endmodule

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ALU VLSI CODE

//ALU

module  alu(s,in1,in2,sel);

input [1:0] in1,in2;

input [3:0] sel;

reg [3:0] d;

output[8:0] s;

reg [8:0] s;

always

case(sel)

         4'b0000:d <= in1&in2;

                4'b0001:d <= in1|in2;

         4'b0010:d <= in1^in2;

                4'b0011:d <= {00,(~(in1^in2))};

                4'b0100:d <= in1-in2;

                4'b0101:d <= in1+in2;

         4'b0110:d <= in1*in2;

                4'b0111:d <= {00,(~(in1))};

                4'b1000:d <= {00,(~(in2))};

                4'b1001:d <= {00,(in1>>1)};

                4'b1010:d <= {00,(in1<<1)};

                4'b1011:d <= {00,(in2>>1)};

                4'b1100:d <= {00,(in2<<1)};

                4'b1101:d <= {00,~(in1&in2)};

                4'b1110:d <= {00,~(in1|in2)};

                4'b1111:d <= {in1,in2};

 endcase

 always

 case(d)

4'b0000: s <= 9'b000000011;

4'b0001: s <= 9'b010011111;

4'b0010: s <= 9'b000100101;

4'b0011: s <= 9'b000001101;

4'b0100: s <= 9'b010011001;

4'b0101: s <= 9'b001001001;

4'b0110: s <= 9'b001000001;

4'b0111: s <= 9'b000011111;

4'b1000: s <= 9'b000000001;

4'b1001: s <= 9'b000001001;

default: s <= 9'b000000000;

endcase

endmodule

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7 SEGMENT VLSI CODE

//7 SEG

module segx(s,d);

input [2:0] d;

output[8:0] s;

reg [8:0] s;

always @(d)

   case(d)

3'b000: s <= 9'b000000011;

3'b001: s <= 9'b010011111;

3'b010: s <= 9'b000100101;

3'b011: s <= 9'b000001101;

3'b100: s <= 9'b010011001;

3'b101: s <= 9'b001001001;

3'b110: s <= 9'b001000001;

3'b111: s <= 9'b000011111;

   endcase

endmodule

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IIR FILTER

//IIR FILTER

module IIR_Filter_8 (Data_out, Data_in, clock, reset);

                parameter          order = 8;

                parameter          word_size_in = 8;                                                                            

                parameter          word_size_out = 2*word_size_in + 2;

                output                  [word_size_out -1: 0] Data_out;

                input                     [word_size_in-1: 0] Data_in;

                input                     clock, reset;

               

                parameter          b0 = 8’d7;            // Feedforward filter coefficients

                parameter          b1 = 8’d17;

                parameter          b2 = 8’d32;

                parameter          b3 = 8’d46;

                parameter          b4 = 8’d52;

                parameter          b5 = 8’d46;

                parameter          b6 = 8’d32;

                parameter          b7 = 8’d17;

                parameter          b8 = 8’d7;

               

                parameter          a1 = 8’d46;          // Feedback filter coefficients

                parameter          a2 = 8’d32;

                parameter          a3 = 8’d17;

                parameter          a4 = 8’d0;

                parameter          a5 = 8’d17;

                parameter          a6 = 8’d32;

                parameter          a7 = 8’d46;

                parameter          a8 = 8’d52;

               

                reg         [word_size_in-1 : 0]        Samples_in [0: order];

                reg         [word_size_in-1 : 0]        Samples_out [1: order];

                wire       [word_size_out-1 : 0]    Data_feedforward;

                wire       [word_size_out-1 : 0]    Data_feedback;

                integer k;

            assign Data_feedforward =  b0 * Samples_in[0]

                                                                + b1 * Samples_in[1]

                                                                + b2 * Samples_in[2]

                                                                + b3 * Samples_in[3]

                                                                + b4 * Samples_in[4]

                                                                + b5 * Samples_in[5]

                                                                + b6 * Samples_in[6]

                                                                + b7 * Samples_in[7]

                                                                + b8 * Samples_in[8];

           assign Data_feedback = a1 * Samples_out [1]

                                                                + a2 * Samples_out [2]

                                                                + a3 * Samples_out [3]

                                                                + a4 * Samples_out [4]

                                                                + a5 * Samples_out [5]

                                                                + a6 * Samples_out [6]

                                                                + a7 * Samples_out [7]

                                                                + a8 * Samples_out [8];

         assign Data_out = Data_feedforward + Data_feedback;

always @ (posedge clock)

                 if (reset == 1)

                                begin

                                                Samples_in [0] <= 0;                      

                                                for (k = 1; k <= order; k = k+1)

                                                                begin

                                                                                Samples_in [k] <= 0;

                                                                                Samples_out [k] <= 0;

                                                                end

                                end

                 else

                                begin

                                                Samples_in [0]  <= Data_in;

                                                Samples_in [1]  <= Samples_in [0] ;

                                                Samples_out [1] <= Data_out;

                                               

                                                for (k = 2; k <= order; k = k+1)

                                                                begin

                                                                                Samples_in [k] <= Samples_in [k-1];                                                                                       Samples_out [k] <= Samples_out [k-1];

                                                                end

                      end

endmodule

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BOOTH MULTIPLIER VLSI CODE

//BOOTH MULTIPLIER

module booth #(parameter WIDTH=4)

 (  input     clk,

    input     enable,

    input    [WIDTH-1:0] multiplier,                           

    input    [WIDTH-1:0] multiplicand,

   output reg [2*WIDTH-1:0] product);

parameter          IDLE       = 2'b00,                                // state encodings

ADD   = 2'b01,

                SHIFT     = 2'b10,

                OUTPUT = 2'b11;

reg  [1:0]              current_state, next_state;  // state registers.

reg  [2*WIDTH+1:0] a_reg,s_reg,p_reg,sum_reg;  // computational values.

reg  [WIDTH-1:0]      iter_cnt;          // iteration count for determining when done.

wire [WIDTH:0]                    multiplier_neg;  // negative value of multiplier

always @(posedge clk)

  if (!enable) current_state = IDLE;

  else         current_state = next_state;

always @* begin

next_state = 2'bx;

case (current_state)

   IDLE: if (enable)  next_state = ADD;

            else  next_state = IDLE;

   ADD:  next_state = SHIFT;

   SHIFT: if (iter_cnt==WIDTH) next_state = OUTPUT;

              else   next_state = ADD;

   OUTPUT:  next_state = IDLE;

endcase

end

// negative value of multiplier.

assign multiplier_neg = -{multiplier[WIDTH-1],multiplier};

// algorithm implemenation details.

always @(posedge clk) begin

  case (current_state)

    IDLE :  begin

                        a_reg    <= {multiplier[WIDTH-1],multiplier,{(WIDTH+1){1'b0}}};

                        s_reg    <= {multiplier_neg,{(WIDTH+1){1'b0}}};

                        p_reg    <= {{(WIDTH+1){1'b0}},multiplicand,1'b0};

                        iter_cnt <= 0;

                     end

    ADD  :  begin

                                case (p_reg[1:0])

                                  2'b01       : sum_reg <= p_reg+a_reg;

                                  2'b10       : sum_reg <= p_reg+s_reg;

                                  2'b00,2'b11 : sum_reg <= p_reg;

                                endcase

                                iter_cnt <= iter_cnt + 1;

                      end

    SHIFT :  begin

                                p_reg <= {sum_reg[2*WIDTH+1],sum_reg[2*WIDTH+1:1]};

                       end

    OUTPUT: product =  p_reg>>1;

endcase

end//always ends

endmodule        //end of source code

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BCD TO SEVEN SEGMENT DISPLAY EMBEDDED C

BCD TO SEVEN SEGMENT DISPLAY

THEORY:

     A 7-segment display is a form of electronic display device for displaying decimal numerals that is an alternative to the more complex dot-matrix displays. Seven-segment displays are widely used in digital clocks, electronic meters, and other electronic devices for displaying numerical information.

The seven segments are arranged as a rectangle of two vertical segments on each side with one horizontal segment on the top, middle, and bottom. The segments of a 7-segment display are referred to by the letters A to G, where the optional DP decimal point (an "eighth segment") is used for the display of non-integer numbers.

BCD I/P	SEGMENT O/P	DISPLAY
	g f e d c b a
0   0   0   0	0 1 1 1 1 1 1	0
0   0   0   1	0 0 0 0 1 1 0	1
0   0   1   0	1 0 1 1 0 1 1	2
0   0   1   1	1 0 0 1 1 1 1	3
0   1   0   0	0 1 1 0 0 1 1	4
0   1   0   1	1 1 0 1 1 0 1	5
0   1   1   0	0 0 1 1 1 1 1	6
0   1   1   1	0 0 0 0 1 1 1	7
1   0   0   0	1 1 1 1 1 1 1	8
1   0   0   1	1 1 0 0 1 1 1	9

CIRCUIT SCHEMATIC & OUTPUT:

PERIPHERAL OUTPUT:

SOURCE CODE:

#include<regx51.h>

sfr out=0xA0; //P3

sfr inp=0x90; //P1

unsigned char temp;

unsigned char const lookup[10]=

           {0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90};

void main()

{

out=0x00;

inp=0xFF;

while(1)

  {

     temp=inp & 0x0F;

     if(temp>=0x0A)

          out=0x00;

     else

          out=~(lookup[temp]);

  }

}

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