UNIVERSAL SHIFT REG VHDL CODE

UNIVERSAL SHIFT REG

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity reg is

port(din:in STD_LOGIC_VECTOR(3 downto 0);

clk,rst: in std_logic;

S:in STD_LOGIC_vector(1 downto 0);

dout:inout std_logic_vector(3 downto 0));

end reg;

architecture Behavioral of reg is

signal msbin,lsbin:STD_LOGIC;

begin

process(clk,rst)

begin

if(rst='1') then

dout <= "0000";

elsif(clk'event and clk='1') then

msbin <= din(3);

lsbin <= din(0);

case S is

when "00" => dout <= dout;--hold

when "01" => dout <= msbin & dout(3 downto 1);-- right shift

when "10" => dout <= dout(2 downto 0) & lsbin;-- left shift

when "11" => dout <= din;-- parallel

when others => dout <= "XXXX";

end case;

end if;

end process;

end Behavioral;