UP/DOWN COUNTER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UP_DOWN_COUNTER is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
UD : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end UP_DOWN_COUNTER;
architecture Behavioral of UP_DOWN_COUNTER is
signal tmp:STD_LOGIC_VECTOR (3 downto 0);
begin
process(clk,rst)
begin
if(rst='1') then
tmp<="0000";
elsif(clk'event and clk='1') then
if(UD='1') then
tmp<=tmp+1;
else
tmp<=tmp-1;
end if;
end if;
end process;
Q <= tmp;
end Behavioral;
please explain this code
ReplyDeleteits simple. the process with clk & rst is the main control block. if rst is 1, then count value is cleared asynchoronously (independent of clock).
ReplyDeletein the rising edge of clk, the count is incremented or decremented depending on 'ud' signal.
if ud=1, UP COUNT else DOWN COUNT