VLSI ,VHDL PROGRAMMING
DESIGN OF 8-TAP FIR FILTER
AIM:
To design an 8-tap FIR
filter in Verilog and to simulate & synthesis the same using XILINX ISE
Tool.
THEORY:
A FIR digital filter forms its output as a weighted sum of present
and past samples of its input, as described by the feed forward difference
equation. FIR filters are moving average filters because their output at any
time index depends on a window containing only the most recent samples of the
input. A FIR filter will have a finite length, non-zero response to a discrete
time impulse. The architecture of a FIR must specify a finite word length for
each of the machine’s arithmetic units and manage the data flow during
operation. The architecture consists of adders, multipliers, shift registers
implementing an Mth order FIR filter. FIR filters are widely used in
practical applications because they can be designed to have a linear phase
characteristics, which ensures that the filter’s output signal is a time
shifted version, but undistorted copy of its input signal. FIR filters cannot
accumulate round off error.
A FIR filter can be described by the
z-domain functional block diagram where each box labeled with z-1
denotes a register cell having a delay of one clock cycle.
Y FIR [n] =
TEST BENCH:
module
tb;
reg
[7:0] datain;
reg clk;
reg rst;
wire [17:0] dataout;
// Instantiate the Unit Under Test
(UUT)
FIR_8thOrder uut (
. Data_out (Data_out),
. Data_in (Data_in),
. clock (clock),
. reset (reset) );
initial begin
Data_in = 0;
clock = 0;
reset = 1;
#100 clock =1;
#100 clock =0;
#100 clock =1; reset =0;
Data_in =8'd1;
#100 clock =0;
#100 clock =1; Data_in =8'd2;
#100 clock =0;
#100 clock =1; Data_in =8'd4;
#100 clock =0;
#100 clock =1; Data_in =8'd6;
#100 clock =0;
#100 clock =1; Data_in =8'd8;
#100 clock =0;
#100 clock =1; datain=8'd10;
#100 clock =0;
#100 clock =1; Data_in =8'd8;
#100 clock =0;
#100 clock =1; Data_in =8'd6;
#100 clock =0;
#100 clock =1; Data_in =8'd4;
end
endmodule
SOURCE CODE:
module FIR_8thOrder (Data_out,
Data_in, clock, reset);
parameter order = 8;
parameter word_size_in = 8;
parameter word_size_out = 2 *
word_size_in + 2;
parameter b0 = 8'd7;
parameter b1 = 8'd17;
parameter b2 = 8'd32;
parameter b3 = 8'd46;
parameter b4 = 8'd52;
parameter b5 = 8'd46;
parameter b6 = 8'd32;
parameter b7 = 8'd17;
parameter b8 = 8'd7;
output [word_size_out-1 : 0]
Data_out;
input [word_size_in-1 : 0] Data_in;
input clock, reset;
reg [word_size_in-1:0] Samples [0 :
order];
integer k;
assign Data_out = b0 * Samples[0]
+ b1 * Samples[1]
+ b2 * Samples[2]
+ b3 * Samples[3]
+ b4 * Samples[4]
+ b5 * Samples[5]
+ b6 * Samples[6]
+ b7 * Samples[7]
+b8 * Samples[8];
always @ (posedge clock)
if (reset == 1)
begin for (k = 0; k <= order; k = k+1)
Samples[k] <= 0;
end
else
begin
Samples[0] <= Data_in;
for( k = 1; k <= order; k = k+1)
Samples[k] <= Samples[k-1];
end
endmodule
RESULT:
Thus the 8th
order FIR filter was designed in Verilog and simulated & synthesized using
XILINX ISE Tool.
DESIGN OF 8-TAP IIR FILTER
AIM:
To design an 8-tap IIR filter in Verilog
and to simulate & synthesis the same using XILINX ISE Tool.
THEORY:
IIR filters are the most general class of
linear digital filters. Their output at a given time step depends on their
inputs and on previously computed outputs. IIR filters are recursive and FIR
filters are non-recursive. The output of an IIR filter is formed in the data
sequence domain as a weighted sum according to Nth order difference
equation.
Yiir[n]
= 
The filter is recursive because the difference equation has feedback.
Consequently, the filter’s response to an impulse may have an infinite
duration.
TEST BENCH:
module
tb;
reg [7:0] Data_in;
reg clock;
reg reset;
wire [17:0] Data_out;
// Instantiate the Unit Under Test
(UUT)
IIR_Filter_8 uut (
.Data_out(Data_out),
.Data_in(Data_in),
.clock(clock),
.reset(reset));
initial begin
Data_in = 0;
clock = 0;
reset = 1;
#100; clock=1;
#100 clock=0;
#100 clock=1; reset =
0;Data_in = 0;
#100 clock=0;
#100 clock=1; Data_in = 1;
#100 clock=0;
#100 clock=1; Data_in = 2;
#100 clock=0;
#100 clock=1; Data_in = 3;
#100 clock=0;
#100 clock=1; Data_in = 4;
#100 clock=0;
#100 clock=1; Data_in = 5;
#100 clock=0;
#100 clock=1; Data_in = 6;
#100 clock=0;
#100 clock=1; Data_in = 7;
#100 clock=0;
#100 clock=1; Data_in = 8;
#100 clock=0;
end
endmodule
SOURCE CODE:
module
IIR_Filter_8 (Data_out, Data_in, clock, reset);
parameter order = 8;
parameter word_size_in = 8;
parameter word_size_out = 2*word_size_in + 2;
output [word_size_out
-1: 0] Data_out;
input [word_size_in-1:
0] Data_in;
input clock,
reset;
parameter b0 = 8'd7; // Feedforward
filter coefficients
parameter b1 = 8'd17;
parameter b2 = 8'd32;
parameter b3 = 8'd46;
parameter b4 = 8'd52;
parameter b5 = 8'd46;
parameter b6 = 8'd32;
parameter b7 = 8'd17;
parameter b8 = 8'd7;
parameter a1 = 8'd46; //
Feedback filter coefficients
parameter a2 = 8'd32;
parameter a3 = 8'd17;
parameter a4 = 8'd0;
parameter a5 = 8'd17;
parameter a6 = 8'd32;
parameter a7 = 8'd46;
parameter a8 = 8'd52;
reg [word_size_in-1
: 0] Samples_in [0: order];
reg [word_size_in-1
: 0] Samples_out [1: order];
wire [word_size_out-1
: 0] Data_feedforward;
wire [word_size_out-1
: 0] Data_feedback;
integer k;
assign Data_feedforward = b0 * Samples_in[0]
+ b1 *
Samples_in[1]
+ b2 *
Samples_in[2]
+ b3 *
Samples_in[3]
+ b4 *
Samples_in[4]
+ b5 *
Samples_in[5]
+ b6 *
Samples_in[6]
+ b7 *
Samples_in[7]
+ b8 *
Samples_in[8];
assign Data_feedback = a1 * Samples_out [1]
+ a2 *
Samples_out [2]
+ a3 *
Samples_out [3]
+ a4 *
Samples_out [4]
+ a5 *
Samples_out [5]
+
a6 * Samples_out [6]
+ a7 *
Samples_out [7]
+ a8 *
Samples_out [8];
assign Data_out = Data_feedforward +
Data_feedback;
always @ (posedge clock)
if (reset == 1)
begin
Samples_in [0] <=
0;
for (k = 1; k <=
order; k = k+1)
begin
Samples_in
[k] <= 0;
Samples_out
[k] <= 0;
end
end
else
begin
Samples_in [0] <= Data_in;
Samples_in [1] <= Samples_in [0] ;
Samples_out [1]
<= Data_out;
for
(k = 2; k <= order; k = k+1)
begin
Samples_in
[k] <= Samples_in [k-1]; Samples_out [k] <=
Samples_out [k-1];
end
end
endmodule
RESULT:
Thus the 8th order IIR filter was designed in Verilog and
simulated & synthesized using XILINX ISE Tool.
DESIGN OF TRAFFIC LIGHT
CONTROLLER
AIM:
To design a traffic light controller in Verilog and to simulate
& synthesis the same using XILINX ISE Tool.
THEORY:
Traffic lights, which may also be known as stoplights, traffic
lamps, traffic signals, stop-and-go lights, robots or semaphore, are signaling
devices positioned at road intersections, pedestrian crossings and other locations to control competing
flows of traffic. Traffic lights have been installed in most cities around the
world. They assign the right
of way to road users by the use of lights in standard colors (red -
yellow - green), using a universal color code.
Typically traffic lights consist of a set of three colored lights:
red, yellow and green. In a typical cycle, Illumination of the green light
allows traffic to proceed in the direction denoted, Illumination of the yellow light denoting, if
safe to do so, prepare to stop short of the intersection, and Illumination of the red signal prohibits any
traffic from proceeding.
TRAFFIC LIGHT
SEQUENCE:
|
SEQUENCE
|
P1
|
P2
|
P3
|
P4
|
PT1
|
PT2
|
|
RESET
|
R
|
R
|
R
|
R
|
R
|
R
|
|
1
|
G
|
R
|
G
|
R
|
R
|
G
|
|
2
|
Y
|
R
|
Y
|
R
|
R
|
R
|
|
3
|
R
|
G
|
R
|
G
|
G
|
R
|
|
4
|
R
|
Y
|
R
|
Y
|
R
|
R
|
TEST BENCH:
module
tb;
// Inputs
reg clk;
reg reset;
// Outputs
wire [4:0] p1;
wire [4:0] p2;
wire [4:0] p3;
wire [4:0] p4;
wire [4:0] pt1;
wire [4:0] pt2;
// Instantiate the Unit Under Test
(UUT)
traflight uut (
.clk(clk),
.reset(reset),
.p1(p1),
.p2(p2),
.p3(p3),
.p4(p4),
.pt1(pt1),
.pt2(pt2)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
#100;
end
initial
clk=1'b0;
always
begin
#5 clk=~clk;
reset=0;
end
endmodule
SOURCE CODE:
module
traflight(clk, reset, p1, p2, p3, p4, pt1, pt2);
input
clk;
input
reset;
output
[4:0] p1;
output
[4:0] p2;
output
[4:0] p3;
output
[4:0] p4;
output
[4:0] pt1;
output
[4:0] pt2;
reg
[4:0] p1;
reg
[4:0] p2;
reg
[4:0] p3;
reg
[4:0] p4;
reg
[4:0] pt1;
reg
[4:0] pt2;
reg
[5:0] sig;
parameter RED = 5'b00111; //Code for RED
parameter GRN = 5'b11000; //Code for GREEN
parameter YLW = 5'b00100; //Code for YELLOW
always @ (posedge clk or posedge reset)
begin
if
(reset == 1'b1)
begin
p1 <= RED;
p2 <= RED; p3 <= RED;
p4 <= RED;
pt1 <= RED;
pt2 <= RED;
sig <= 6'b000000;
end
else
begin
sig
<= sig + 1;
case
(sig[5:0])
6'b000000
: begin
p1 <= GRN;
p2 <= RED;
p3 <= GRN;
p4 <= RED;
pt1
<= RED;
pt2
<= GRN;
end
6'b000001
: begin
p1 <= YLW;
p2 <= RED;
p3 <= YLW;
p4 <= RED;
pt1
<= RED;
pt2
<= RED;
end
6'b000001
: begin
p1 <= RED;
p2 <= GRN;
p3 <= RED;
p4 <= GRN;
pt1
<= GRN;
pt2
<= RED;
end
6'b000011
: begin
p1 <= RED;
p2
<= YLW;
p3 <= RED;
p4 <= YLW;
pt1
<= RED;
pt2
<= RED;
end
6'b000100
: sig <= 6'b000000;
endcase
end
end
endmodule
RESULT:
Thus a traffic light
controller was designed in Verilog and simulated & synthesized using XILINX
ISE Tool.
RULES FOR BIT-PAIR (RADIX-4)
RECODING OF A 2S COMPLEMENT NUMBER
|
mi+1
|
mi
|
mi-1
|
Code
|
BRCi+1
|
BRCi
|
Value
|
Actions
|
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
Shift by 2
|
|
0
|
0
|
1
|
1
|
0
|
1
|
+1
|
Add, shift by 2
|
|
0
|
1
|
0
|
2
|
0
|
1
|
+1
|
Add, shift by 2
|
|
0
|
1
|
1
|
3
|
1
|
0
|
+2
|
Shift by 1 , Add, Shift by 1
|
|
1
|
0
|
0
|
4
|
1
|
0
|
-2
|
Shift by 1 , Subtract, Shift by 1
|
|
1
|
0
|
1
|
5
|
0
|
1
|
-1
|
Subtract, shift by 2
|
|
S
|
1
|
0
|
6
|
0
|
1
|
-1
|
Subtract, shift by 2
|
|
1
|
1
|
1
|
7
|
0
|
0
|
0
|
Shift by 2
|
DESIGN OF MODIFIED BOOTH
MULTIPLIER
AIM:
To design a modified booth multiplier in Verilog and to simulate
& synthesis the same using XILINX ISE Tool.
THEORY:
Bit Pair Encoding (BPE) is a
modified booth multiplication technique where the number of additions (no of
partial products so generated) is reduced from n to n/2 for an ‘n’ bit
multiplier.
Bit pair encoding of
a multiplier examines 3 bits at a time and creates a 2-bit code whose values
determines whether to
Add the multiplicand
Shift the multiplicand by 1 bit and then add
Subtract the multiplicand (adding
2s complement of the multiplicand to the product)
Shift the 2s complement of the multiplicand to the left by 1 bit and
then add
To only shift the multiplicand to the location corresponding to the
next bit-pair.
The first step of BPE algorithm is seeded with a value of 0 in the
register cell to the right of the LSB of the multiplier word. Subsequent
actions depend on the value of the recoded bit-pair. The index ‘i’ increments
by two until the word is exhausted. If
the word contains an odd number of bits, its sign bit must be extended by one
bit to accommodate the recoding scheme. Recoding divides the multiplier word by
2, so the number of possible additions is reduced by a factor of 2. The rules
for bit-pair encoding are summarized in the table provided in the left.
TEST BENCH:
module
testbench;
// Inputs
reg clk;
reg enable;
reg [3:0] multiplier;
reg [3:0] multiplicand;
// Outputs
wire done;
wire [7:0] product;
// Instantiate the Unit Under Test
(UUT)
booth uut (
.clk(clk),
.enable(enable),
.multiplier(multiplier),
.multiplicand(multiplicand),
.product(product)
);
initial
clk=1'b0;
always
#5 clk=~clk;
initial begin
enable = 0;
multiplier = 0;
multiplicand = 0;
#250 enable = 1;
multiplier = 4'b0011;
multiplicand = 4'b0011;
#250 enable = 1;
multiplier = 4'b1010;
multiplicand = 4'b0100;
#250 enable = 1;
multiplier = 4'b0010;
multiplicand = 4'b1001;
#250 enable = 1;
multiplier = 4'b1010;
multiplicand = 4'b1100;
#250;
end
endmodule
//end of testbench
SOURCE CODE:
module
booth #(parameter WIDTH=4)
( input clk,
input enable,
input [WIDTH-1:0] multiplier,
input [WIDTH-1:0] multiplicand,
output
reg [2*WIDTH-1:0] product);
parameter IDLE = 2'b00, // state encodings
ADD = 2'b01,
SHIFT = 2'b10,
OUTPUT
= 2'b11;
reg [1:0] current_state,
next_state; // state registers.
reg [2*WIDTH+1:0] a_reg,s_reg,p_reg,sum_reg; //
computational values.
reg [WIDTH-1:0] iter_cnt; //
iteration count for determining when done.
wire
[WIDTH:0] multiplier_neg; //
negative value of multiplier
always
@(posedge clk)
if (!enable) current_state = IDLE;
else
current_state = next_state;
always
@* begin
next_state = 2'bx;
case (current_state)
IDLE: if (enable) next_state =
ADD;
else next_state
= IDLE;
ADD: next_state = SHIFT;
SHIFT: if (iter_cnt==WIDTH) next_state = OUTPUT;
else next_state = ADD;
OUTPUT: next_state = IDLE;
endcase
end
// negative value of
multiplier.
assign
multiplier_neg = -{multiplier[WIDTH-1],multiplier};
// algorithm
implemenation details.
always
@(posedge clk) begin
case (current_state)
IDLE :
begin
a_reg <=
{multiplier[WIDTH-1],multiplier,{(WIDTH+1){1'b0}}};
s_reg <= {multiplier_neg,{(WIDTH+1){1'b0}}};
p_reg <=
{{(WIDTH+1){1'b0}},multiplicand,1'b0};
iter_cnt <= 0;
end
ADD
: begin
case (p_reg[1:0])
2'b01
: sum_reg <= p_reg+a_reg;
2'b10
: sum_reg <= p_reg+s_reg;
2'b00,2'b11 : sum_reg <= p_reg;
endcase
iter_cnt <= iter_cnt + 1;
end
SHIFT :
begin
p_reg <=
{sum_reg[2*WIDTH+1],sum_reg[2*WIDTH+1:1]};
end
OUTPUT: product = p_reg>>1;
endcase
end//always ends
endmodule //end of
source code
RESULT:
Thus a modified booth
multiplier was designed in Verilog and simulated & synthesized using XILINX
ISE Tool.
DESIGN AND IMPLEMENTATION OF
SEVEN SEGMENT DISPLAY
AIM:
To write the code for seven segment display
in verilog and implement that code using XILINX Spartan kit.
THEORY:
A seven-segment display
(SSD), or seven-segment indicator,
is a form of electronic display device for
displaying decimal numerals that is an alternative to the more
complex dot-matrix displays. Seven-segment displays are
widely used in digital clocks,
electronic meters, and other electronic devices for displaying numerical
information.
Each of the numbers 0, 6, 7 and 9 may be represented by two or more different
glyphs on seven-segment displays. The seven segments are arranged as a rectangle of two vertical segments on each side
with one horizontal segment on the top, middle, and bottom.
STEPS TO IMPLEMENT THE DESIGN IN SPARTAN 3E FPGA KIT:
1. Open Xilinx ISE Project Navigator.
2. Open new project and give a name for
it & save in desired location.
3. Type the source code & verify
your code can be synthesized in the Spartan-3E FPGA.
4. Assign Pin Connections using Assign
Pin Packages on the left under User Constraints and save it as Use
Constraint File (.ucf).
5. Run implementation by double
clicking on “Implement Design” on the left. Implementation takes the design and
translates, maps, and routes design to the FPGA chip.
6. The
final step in
this stage is generating the
*.bit file. The bit file (.bit)
is what is put onto the FPGA chip to program it.
7. Then click on Configure Device to
program the bit file to FPGA chip.
8. An
amber LED on
the FPGA board
should light up
to show that
the chip was
successfully programmed.
PIN ASSIGNMENT:
NET "d<0>" LOC = "p142" ;
NET "d<1>" LOC = "p136" ;
NET "d<2>" LOC = "p130" ;
NET "s<0>" LOC = "p19" ;
NET "s<1>" LOC = "p18" ;
NET "s<2>" LOC = "p16" ;
NET "s<3>" LOC = "p15" ;
NET "s<4>" LOC = "p12" ;
NET "s<5>" LOC = "p11" ;
NET "s<6>" LOC = "p9" ;
NET "s<7>" LOC = "p8" ;
NET "s<8>" LOC = "p3" ;
SOURCE CODE:
module segx(s,d);
input [2:0] d;
output[8:0] s;
reg [8:0] s;
always @(d)
case(d)
3'b000: s <= 9'b000000011;
3'b001: s <= 9'b010011111;
3'b010: s <= 9'b000100101;
3'b011: s <= 9'b000001101;
3'b100: s <= 9'b010011001;
3'b101: s <= 9'b001001001;
3'b110: s <= 9'b001000001;
3'b111: s <= 9'b000011111;
endcase
endmodule
RESULT:
Thus the verilog code for seven segment
display is written and implemented using XILINX Spartan kit.
DESIGN AND IMPLEMENTATION OF ALU
AIM:
To write the code for seven segment with ALU in verilog and
implement that code using XILINX Spartan kit.
THEORY:
In computing,
an arithmetic logic unit (ALU) is a digital
circuit that performs arithmetic and logical
operations. The ALU is a fundamental building block of the central processing unit of a computer, and
even the simplest microprocessors contain one for purposes such as
maintaining timers. The processors found inside modern CPUs and graphics
processing units (GPUs) accommodate very powerful and very
complex ALUs; a single component may contain a number of ALUs.
Most of a processor's operations are performed by one or more ALUs.
An ALU loads data from input registers, an external Control Unit
then tells the ALU what operation to perform on that data, and then the ALU
stores its result into an output register. The Control Unit
is responsible for moving the processed data between these registers, ALU and
memory.
Most ALUs can perform the following operations:
·
Integer arithmetic operations (addition,
subtraction,
and sometimes multiplication and division, though this is more expensive)
·
Bit-shifting operations (shifting or rotating a
word by a specified number of bits to the left or right, with or without sign
extension). Shifts can be seen as multiplications and divisions by a
power of two.
PIN ASSIGNMENT:
#PACE: Start of PACE I/O Pin
Assignments
NET "sel<0>" LOC
= "p72" ;
NET "sel<1>" LOC
= "p71" ;
NET "sel<2>" LOC = "p58" ;
NET "sel<3>" LOC
= "p57" ;
NET "s<0>" LOC
= "p19" ;
NET "s<1>" LOC
= "p18" ;
NET "s<2>" LOC
= "p16" ;
NET "s<3>" LOC
= "p15" ;
NET "s<4>" LOC
= "p12" ;
NET "s<5>" LOC
= "p11" ;
NET "s<6>" LOC
= "p9" ;
NET "s<7>" LOC
= "p8" ;
NET "s<8>" LOC
= "p4" ;
NET "in1<1>" LOC
= "p91" ;
NET "in1<0>" LOC
= "p101" ;
NET "in2<1>" LOC
= "p194" ;
NET "in2<0>" LOC
= "p204" ;
SOURCE CODE:
module alu(s,in1,in2,sel);
input [1:0] in1,in2;
input [3:0] sel;
reg [3:0] d;
output[8:0] s;
reg [8:0] s;
always
case(sel)
4'b0000:d <= in1&in2;
4'b0001:d
<= in1|in2;
4'b0010:d <= in1^in2;
4'b0011:d
<= {00,(~(in1^in2))};
4'b0100:d
<= in1-in2;
4'b0101:d
<= in1+in2;
4'b0110:d <= in1*in2;
4'b0111:d
<= {00,(~(in1))};
4'b1000:d
<= {00,(~(in2))};
4'b1001:d
<= {00,(in1>>1)};
4'b1010:d
<= {00,(in1<<1)};
4'b1011:d
<= {00,(in2>>1)};
4'b1100:d
<= {00,(in2<<1)};
4'b1101:d
<= {00,~(in1&in2)};
4'b1110:d
<= {00,~(in1|in2)};
4'b1111:d
<= {in1,in2};
endcase
always
case(d)
4'b0000: s <= 9'b000000011;
4'b0001: s <= 9'b010011111;
4'b0010: s <= 9'b000100101;
4'b0011: s <= 9'b000001101;
4'b0100: s <= 9'b010011001;
4'b0101: s <= 9'b001001001;
4'b0110: s <= 9'b001000001;
4'b0111: s <= 9'b000011111;
4'b1000: s <= 9'b000000001;
4'b1001: s <= 9'b000001001;
default: s <= 9'b000000000;
endcase
endmodule
RESULT:
Thus the verilog code
for seven segment display with ALU is written and implemented using XILINX
Spartan kit.
DESIGN AND IMPLEMENTATION OF
RAM
AIM:
To write the code for RAM in verilog and implement that code using
XILINX Spartan kit.
THEORY:
Random access memory (RAM) is a form of computer data storage. Today, it takes the
form of integrated circuits that allow stored data to be accessed in
any order with a worst case performance of constant
time RAM is often associated with volatile
types of memory (such as DRAM memory
modules), where its stored information is lost if the power is removed.
Many other types of non-volatile memory are RAM as well, including most types
of ROM and a type of flash
memory called NOR-Flash
The two main forms of modern
RAM are static RAM (SRAM) and dynamic RAM (DRAM). In static RAM, a bit of data is stored
using the state of a flip-flop. This form of RAM is more
expensive to produce, but is generally faster and requires less power than DRAM
and, in modern computers, is often used as cache memory for the CPU. DRAM stores a bit of data using a
transistor and capacitor pair, which together comprise a memory cell. The
capacitor holds a high or low charge (1 or 0, respectively), and the transistor
acts as a switch that lets the control circuitry on the chip read the
capacitor's state of charge or change it. As this form of memory is less
expensive to produce than static RAM, it is the predominant form of computer
memory used in modern computers.
PIN ASSIGNMENT:
#PACE: Start of PACE I/O Pin
Assignments
NET "addr<0>" LOC =
"p101" ;
NET "addr<1>" LOC = "p91" ;
NET "addr<2>" LOC =
"p39" ;
NET "addr<3>" LOC =
"p72" ;
NET "addr<4>" LOC =
"p71" ;
NET "di<0>" LOC
= "p204" ;
NET "di<1>" LOC
= "p194" ;
NET "di<2>" LOC
= "p184" ;
NET "di<3>" LOC
= "p183" ;
NET "dout<0>" LOC =
"p133" ;
NET "dout<1>" LOC =
"p129" ;
NET "dout<2>" LOC =
"p127" ;
NET "dout<3>" LOC =
"p122" ;
NET "en" LOC
= "p110" ;
NET "we" LOC
= "p124" ;
SOURCE CODE:
module ram( we, en, addr, di, dout);
input we;
input en;
input [4:0] addr;
input [3:0] di;
output [3:0] dout;
reg [3:0] RAM [31:0];
reg [3:0] dout;
always @(en)
begin
if (en) begin
if (we)
RAM[addr] <= di;
else
dout <= RAM[addr];
end
end
endmodule
RESULT:
Thus the verilog code
for RAM is written and implemented using XILINX Spartan kit.
VHDL PROGRAMMING
DESIGN OF UNIVERSAL
SHIFT REGISTER
AIM:
To
design a universal shift register in vhdl and to simulate & synthesis the
same using XILINX ISE Tool.
THEORY:
In digital circuits, a shift register is a cascade of flip
flops, sharing the same clock, which has the output of anyone but the last
flip-flop connected to the "data" input of the next one in the chain,
resulting in a circuit that shifts by one position the one-dimensional "bit
array" stored in it, shifting in
the data present at its input and shifting
out the last bit in the array, when enabled to do so by a transition of
the clock input. More generally, a shift
register may be multidimensional; such that its "data in"
input and stage outputs are themselves bit arrays: this is implemented simply
by running several shift registers of the same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs.
These are often configured as serial-in,
parallel-out (SIPO) or as parallel-in,
serial-out (PISO). There are also types that have both serial and
parallel input and types with serial and parallel output. There are also bi-directional shift registers which
allow shifting in both directions: L→R or R→L.
The serial input and last output of a shift register can also be connected to
create a circular shift register.
SOURCE CODE:
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_arith.ALL;
use
IEEE.STD_LOGIC_unsigned.ALL;
entity
reg is
port(din:in
STD_LOGIC_VECTOR(3 downto 0);
clk,rst:
in std_logic;
S:in
STD_LOGIC_vector(1 downto 0);
dout:inout
std_logic_vector(3 downto 0));
end
reg;
architecture
Behavioral of reg is
signal
msbin,lsbin:STD_LOGIC;
begin
process(clk,rst)
begin
if(rst='1')
then
dout
<= "0000";
elsif(clk'event
and clk='1') then
msbin
<= din(3);
lsbin
<= din(0);
case
S is
when
"00" => dout <= dout;--hold
when
"01" => dout <= msbin & dout(3 downto 1);-- right shift
when
"10" => dout <= dout(2 downto 0) & lsbin;-- left shift
when
"11" => dout <= din;-- parallel
when
others => dout <= "XXXX";
end
case;
end
if;
end
process;
end
Behavioral;
RESULT:
Thus
the universal shift register is designed in vhdl and simulated & synthesized
using XILINX ISE Tool.
DESIGN
OF UP DOWN COUNTER
AIM:
To
design an up down counter in vhdl and to simulate & synthesis the same
using XILINX ISE Tool.
THEORY:
In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal.
A counter that can change state in
either direction, under the control of an up/down selector input, is known as
an up/down counter. When the selector is in the up state, the counter
increments its value.When the selector is in the down state, the counter
decrements the count.
SIMULATION RESULT:
SOURCE CODE:
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
UP_DOWN_COUNTER is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
UD : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end
UP_DOWN_COUNTER;
architecture
Behavioral of UP_DOWN_COUNTER is
signal
tmp:STD_LOGIC_VECTOR (3 downto 0);
begin
process(clk,rst)
begin
if(rst='1')
then
tmp<="0000";
elsif(clk'event
and clk='1') then
if(UD='1')
then
tmp<=tmp+1;
else
tmp<=tmp-1;
end
if;
end
if;
end
process;
Q
<= tmp;
end
Behavioral;
RESULT:
Thus
the up down counter is designed in vhdl and simulated & synthesized using XILINX
ISE Tool.
DESIGN OF CYCLIC
COMBINATIONAL
CIRCUITS
AIM:
To
design cyclic combinational circuits in VHDL and to simulate & synthesis
the same using XILINX ISE Tool.
THEORY:
A
collection of logic gates forms a combinational circuit if the outputs can be
described as Boolean functions of the current input values. The accepted wisdom is that combinational
circuits must have acyclic (i.e., loop-free or feed-forward) topologies. The cyclic combinational circuits are the
circuits with loops or feedback paths. The technique, applicable in the
substitution phase of logic synthesis, optimizes a multilevel description,
introducing feed-back and potentially reducing the size of the resulting
network.
A seven-segment display (SSD), or seven-segment indicator, is a form of electronic display device for displaying decimal
numerals that is an alternative to the more
complex dot-matrix displays. Seven-segment displays
are widely used in digital clocks, electronic meters, and other
electronic devices for displaying numerical information.
The seven segments are arranged as a
rectangle
of two vertical segments on each side with one horizontal segment on the top,
middle, and bottom. Additionally, the seventh segment bisects the rectangle
horizontally. There are also fourteen-segment
displays and sixteen-segment
displays (for full alphanumeric);
however, these have mostly been replaced by dot-matrix
displays.
SOURCE CODE:
------------------------------- 7
SEGMENT-------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sevseg is
port(x: in std_logic_vector(3 downto
0);
a,b,c,d,e,f,g: inout std_logic);
end sevseg;
architecture Behavioral of sevseg is
signal a1,a2,b1,d1,f1,g1:std_logic;
begin
a1<=(not x(3)) and x(2) and x(0);
a2<=(not x(2)) and (( x(3) and
(not x(1))) or d);
a<= a1 or a2;
b1<=((not x(2)) or ((not x(1))
and (not x(0))));
b<=(b1 and c) or ((not x(3)) and
(not(f)));
c<=((not x(3)) and (not (e))) or
f;
d1<=(x(1) or (not x(0))) and (not
x(2)) and b;
d<=d1 or ((not x(3)) and (not
b));
e<=(not x(0)) and d;
f1<=(not x(3)) and (not x(0)) and
(not a);
f<= f1 or ((not x(1)) and a);
g1<=(x(3) or x(2)) and f;
g<=g1 or (x(1) and d);
end Behavioral;
--------------------------------- COMPARATOR -------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cycomp is
port(C,D: in std_logic_vector(1 downto 0);
M,N,O: out std_logic);
end cycomp;
architecture Behavioral of cycomp is
component orgcomp
port(A,B: in std_logic_vector(1 downto 0);
X,Y,Z: out std_logic);
end component;
signal L,E,G :std_logic;
signal h,i,j,k,p
:std_logic;
begin
co:orgcomp port map(C,D,G,E,L);
h<=not L;
i<=C(1) and (not D(1));
j<=C(0) and (not D(0));
M<= h and (i or j);
k<=((((not C(1)) or D(1)) and D(0)) and (not (E)));
N<= ((not C(1)) and D(1) ) or k;
p<= ((C(0) xnor D(0)) and ((not C(1)) and (not D(1))));
O<= p or (C(1) and (not (G)) and( C(0) or (not(D(0)))));
end Behavioral;
--ORGCOMP: code
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
orgcomp is
port(A,B:
in std_logic_vector(1 downto 0);
X,Y,Z:
out std_logic);
end
orgcomp;
architecture
Behavioral of orgcomp is
begin
COMP:PROCESS(A,B)
begin
if
(A>B) then
X<='1';
Y<='0';
Z<='0';
elsif
A=B then
X<='0';
Y<='1';
Z<='0';
elsif
A<B then
X<='0';
Y<='0';
Z<='1';
end
if;
END
PROCESS COMP;
end
Behavioral;
RESULT:
Thus the cyclic combinational circuit is designed in vhdl and simulated
& synthesized using XILINX ISE Tool.
someone have the VHDL code for FIR filter??
ReplyDelete