AVR - SPI - Serial Pheripheral Interface Tutorial - ATmega8 Code

AVR - SPI - Serial Pheripheral Interface Tutorial - C Code Example - ATmega8 Code

AVR ATMega8 microcontroller has inbuilt SPI module. First SPI intorduction, and then let us see how to use it.

Serial Peripheral Interface Bus or SPI  bus is a synchronous serial data link standard, named by Motorola, that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. SPI is often referred to as SSI

 ·         SCLK: serial clock (output from master);

·         MOSI: master output, slave input (output from master);

·         MISO: master input, slave output (output from slave);

·         SS: slave select (active low, output from master).

To begin a communication, the bus master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 1–100 MHz.

The master then transmits the appropriate chip select bit for the desired chip to a logic 0. A logic 0 is transmitted because the chip select line is active low, meaning its off state is a logic 1; on is asserted with a logic 0. If a waiting period is required (such as for analog-to-digital conversion), then the master must wait for at least that period of time before starting to issue clock cycles.

During each SPI clock cycle, a full duplex data transmission occurs:

·         the master sends a bit on the MOSI line; the slave reads it from that same line

·         the slave sends a bit on the MISO line; the master reads it from that same line

Not all transmissions require all four of these operations to be meaningful but they do happen.

Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a ring. Data is usually shifted out with the most significant bit first, while shifting a new least significant bit into the same register. After that register has been shifted out, the master and slave have exchanged register values. Then each device takes that value and does something with it, such as writing it to memory. If there is more data to exchange, the shift registers are loaded with new data and the process repeats.

Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops toggling its clock. Normally, it then deselects the slave. Transmissions often consist of 8-bit words. Every slave on the bus that hasn't been activated using its chip select line must disregard the input clock and MOSI signals, and must not drive MISO. The master must select only one slave at a time.

Clock polarity and phase

In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Freescale's SPI Block Guide names these two options as CPOL and CPHA respectively, and most vendors have adopted that convention.

       The timing diagram is shown to the right. The timing is further described below and applies to both the master and the slave device.

v  At CPOL=0 the base value of the clock is zero

Ø  For CPHA=0, data is captured on the clock's rising edge (low→high transition) and data is propagated on a falling edge (high→low clock transition).

Ø  For CPHA=1, data is captured on the clock's falling edge and data is propagated on a rising edge.

v  At CPOL=1 the base value of the clock is one (inversion of CPOL=0)

Ø  For CPHA=0, data is captured on clock's falling edge and data is propagated on a rising edge.

Ø  For CPHA=1, data is captured on clock's rising edge and data is propagated on a falling edge.

That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle. For all CPOL and CPHA modes, the initial clock value must be stable before the chip select line goes active.

The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle. This adds more flexibility to the communication channel between the master and slave.

Mode numbers

The combinations of polarity and phases are often referred to as modes which are commonly numbered according to the following convention, with CPOL as the high order bit and CPHA as the low order bit:

Mode	CPOL	CPHA
0	0	0
1	0	1
2	1	0
3	1	1

Another commonly used notation represents the mode as a (CPOL, CPHA) tuple; e.g., the value '(0, 1)' would indicate CPOL=0 and CPHA=1

Independent slave SPI configuration

Independent slave configuration, there is an independent chip select line for each slave. This is the way SPI is normally used. Since the MISO pins of the slaves are connected together, they are required to be tri-state pins.

AVR SPI registers

SPI Control register:

SPCR	7	6	5	4	3	2	1	0
	SPIE	SPE	DORD	MSTR	CPOL	CPHA	SPR1	SPR0

SPIE    - SPI interrupt enable bit. 1-> enable, 0-> disable

SPE     - SPE module enable bit. 1-> enable, 0-> disable

DORD  - Data order. 1-> MSB sent first, 0-> LSB sent first

SPI Status register:

SPSR	7	6	5	4	3	2	1	0
	SPIF	WCOL	-	-	-	-	-	SPI2X

SPIF    - SPI interrupt flag. Set by hardware on data transmission complete, data received, error 

            occurred.

 WCOL  - Write collision flag. Set when SPDR is accessed while data transmission is in progress.

SPI2X  - SPI double speed select bit. 0-> normal, 1-> double speed

SPI2X	SPR1	SPR0	Fclk
0	0	0	Fosc/4
0	0	1	Fosc/16
0	1	0	Fosc/64
0	1	1	Fosc/128
1	0	0	Fosc/2
1	0	1	Fosc/8
1	1	0	Fosc/32
1	1	1	Fosc/64

NOTE: Fosc is the MCU Oscillator frequency.

SPI Data register:

SPDR	7	6	5	4	3	2	1	0
	B7	B6	B5	B4	B3	B2	B1	B0

 In this example, the character is received by MASTER through UART & transmitted to slave by SPI. The SLAVE is configured to generate an interrupt on reception of a SPI byte. The interrupt handler sends the received character on UART.

  

SPI MASTER DEVICE CODE:

  SPI ENABLE:

          // Set MOSI and SCK output, all others input

          DDRB = (1<<5)|(1<<3)|(1<<2);

          // Enable SPI, Master, set clock rate fck/16    SPI MODE 0

          SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

  UART INITIALIZATION:

          uart_init(9600);        //Initialise the USART Module with the given Baudrate

SPI SLAVE DEVICE CODE:

          // Set MOSI and SCK output, all others input

          DDRB = 0x14;

          // Enable SPI, Master, set clock rate fck/16, SPI MODE 1

          SPCR = (1<<SPE)|(1<<SPIE)|(1<<CPHA);

          uart_init(9600);        //Initialise the USART Module with the given Baudrate

          sei();//enable global interrupt

ISR OF SPI DATA HANDLING:

ISR(SPI_STC_vect)

{

          ch=SPDR;

          uart_putc(ch);

}

 The UART functions are as in the previous tutorial. Click to see UART example.

Click to download the SPI MASTER and SLAVE C file. It is complied by AVRStudio (4) & simulated using Protues software.

Proteus Output:

Schematic

Master & slave configuration

Initial screen.

Text is typed in master TX terminal  & it is displayed on slave RX terminal

Click to download  

PDF document

Project Files

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