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PTM releases a new set of models for high-performance applications (PTM HP), incorporating high-k/metal gate and stress effect.
- 32nm PTM HP model
- 45nm PTM HP model
PTM releases a new version for sub-45nm bulk CMOS, providing new modeling features of metal gate/high-k, gate leakage, temperature effect, and body bias.
- 32nm PTM model for metal gate/high-k CMOS
- 45nm PTM model for metal gate/high-k CMOS
PTM extends the effort to post-Si devices. The first release is for carbon nano-tube FET (CNT-FET).
- Verilog-A based model card for CNT-FET
PTM for bulk CMOS is released, for 22nm node.
- 22nm BSIM4 model card for bulk CMOS
A new generation of PTM for bulk CMOS is released, for 130nm to 32nm nodes. It captures the latest technology advances and achieves better scalability and continuity across technology nodes.
- 32nm BSIM4 model card for bulk CMOS
- 45nm BSIM4 model card for bulk CMOS
- 65nm BSIM4 model card for bulk CMOS
- 90nm BSIM4 model card for bulk CMOS
- 130nm BSIM4 model card for bulk CMOS
- 180nm BSIM3 model card for bulk CMOS
References
- S. Sinha, G. Yeric, V. Chandra, B. Cline, Y. Cao, "Exploring sub-20nm FinFET design with predictive technology models," to be published at DAC, 2012.
- A. Balijepalli, S. Sinha, Y. Cao, "Compact modeling of carbon nanotube transistor for early stage process-design exploration," ISLPED, pp. 2-7, 2007.
- W. Zhao, Y. Cao, "New generation of Predictive Technology Model for sub-45nm early design exploration," IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816-2823, November 2006.
- Y. Cao, T. Sato, D. Sylvester, M. Orshansky, C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," pp. 201-204, CICC, 2000.
