MODELSIM TUTORIAL – WORKING WITH TESTBENCH – GETTING STARTED

GETTING STARTED WITH MENTOR GRAPH MODELSIM SE 6

              Mentorgraph Modelsim is an simulation tool and is being used in many industries for simulation and code verification. This tool can be used for simulation along with Xilinx (upto ISE 9.x). But recent Xilinx edition have withdrawn other third-party simulation & addon support.

              But this is an easy tool when you need to just simulate and verify the code & its correctness. But the steps are likely to be confusing. Here we present an example for creating a new design file and simulating it in Modelsim version SE6.

1.      Open ModelSim SE6.

2.      Then, goto FILE->CHANGE DIRECTORY  to change the current working directory.

3.      Choose your required folder. Here I choose "C:\My Projects".

4.      Now create a new work library by, FILE-> NEW-> LIBRARY.

5.      In create, select 'a new lib & logical map to it' and give Library Name and Library Physical Name as "work".

6.      To create a new verilog file, choose FILE->NEW-> SOURCE-> VERILOG

7.      Type the verilog code and save it. Here a positive edge triggered D flip flop synchronous reset and preset is used.

module dffr_pr (d,clk,preb,rstb, q,qb);
  input d,clk,preb,rstb;
  output reg q;
  output qb;
    assign qb=~q;
    always @ (posedge clk) begin
    if(rstb==0)
      q=0;
    else if(preb==0)
            q=1;
         else
            q=d;
  end
  endmodule

8.      Now compile the code by, COMPILE->COMPILE. In the pop-up window select your code file and compile it. If done successfully, we can see the report in transcript window. And the module will be added under the work directory.

9.      To simulate the module double click the module name under the Library window. This will start simulating with full optimization. Check the report in transcript window.

10.  If you can't see a wave window, choose VIEW->WAVE. This opens the wave window. It will be empty without any signals.

11.  To add the signals to it, under Objects window, right click on required signals and select             ADD->TO WAVE-> SELECTED SIGNALS. Then those will be added to the wave window. This can also be performed by typing "add wave *" in the transcript window.

12.  Next we have to assign the values to the signals. Just right click the required signal and choose req option and value for it. All timing by default are in ns

Type	Transcipt command	Procedure
Clock	force -freeze sim:/dffr_pr/clk 1 5, 0 {30 ns} -r 50	right click->clock Offset: 5     Duty cycl: 50 Preiod: 50  rising edge
Net	force -freeze sim:/dffr_pr/preb 1 0	right click->force put desired binary value

The transcript commands for simulating the above DFF code is,

force -freeze sim:/dffr_pr/clk 1 5, 0 {30 ns} -r 50
force -freeze sim:/dffr_pr/preb 1 0
force -freeze sim:/dffr_pr/rstb 1 0
force -freeze sim:/dffr_pr/rstb 0 0
run 50ns
force -freeze sim:/dffr_pr/rstb 1 0
force -freeze sim:/dffr_pr/d 1 0
run 50ns
force -freeze sim:/dffr_pr/d 0 0
run 50ns
force -freeze sim:/dffr_pr/preb 0 0
run 50ns
force -freeze sim:/dffr_pr/rstb 0 0
run 50ns
force -freeze sim:/dffr_pr/preb 1 0
force -freeze sim:/dffr_pr/rstb 1 0
run 50ns

Just copy and paste these lines in the transcript window & hit enter. The waveforms appear in the Wave window. The transcript shown here includes all the possible input combinations of the DFF. Note that the RSTB is the high priority signal, then PREB and finally the DATA.  Here a 5ns offset to clock is added. It is similar to setup time.

13.  To quit simulation, select SIMULATE->END SIMULATION or type "quit –sim" in transcript window

14.  A testbench file can also be used to simulate a code.

15.  For that, both main module and the test bench module has to be compiled. Then simulate the TEST BENCH file and just run for required time.

 

 

 

The verilog testbench file for the DFF is as follows,

       module tb_DFFX;

//assign default values
    reg d= 1'b0;
    reg clk = 1'b0;
    reg preb = 1'b1;
    reg rstb = 1'b0;
    wire q;
    wire qb;
 
    parameter PERIOD = 50;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 5;
 
    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end
 
    dffr_pr UUT (
        .clk(clk),
        .d(d),
        .rstb(rstb),
        .preb(preb),
        .q(q),
        .qb(qb));
 
    initial begin
           #100; // -------------  Current Time:  100ns

rstb = 1'b1;//reset completes
d= 1'b1;
#100;
d= 1'b0;
#150;
preb= 1'b0;
#100;
rstb= 1'b0;
#150;
preb=1'b1;
rstb= 1'b1;

    end
endmodule

 

The transcript for compiling & simulating the test bench file is

vlog {C:/My Projects/dffr_pr.v} vlog {C:/My Projects/TB_DFF.v} vsim -novopt work.tb_DFF add wave * run 700ns

compile DFF compile Test Bench simulate TB without optimization add all signals run upto 700ns

Click here to goto Verilog Tutorials.

If you have any queries regarding this, plz feel free to ask us through admin@elecdude.com. ;-) 

Readers comments are encouraged.
This helps us to do much more better.
Thankyou.