VERILOG TASK AND FUNCTIONS - SYNTAX - EXAMPLE

                Task and Functions in verilog are similar to each other but has many differences in their operation. These can be used to do a simple operations that can be called repeatedly, but instead of instantiating a module, these could be used. Here is the syntax and example for the Verilog Task and function. 

FUNCTION 

 A Verilog HDL function is the same as a task, with very little differences, like function cannot drive more than one output, can not contain delays.

·         functions can not include timing delays, like posedge, negedge, # delay, which means that functions should be executed in "zero" time delay.

·         functions can have any number of inputs but only one output.

·         The variables declared within the function are local to that function.  

·         functions can call other functions, but can not call tasks.

·         functions can be used for modeling combinational logic.

module  function_calling(a, b, c, d, e, f);

input a, b, c, d, e ;

output f;

wire f;

`include "myfunction.v"

                 

assign f =  (myfunction (a,b,c,d)) ? e :0;

endmodule

myfunction.v

function  myfunction;

input a, b, c, d;

begin

  myfunction = ((a+b) + (c-d));

end

endfunction

 `include command is used to include a file from the current directory.

TASK

·         tasks can include timing delays, like posedge, negedge, # delay and wait.

·         tasks can have any number of inputs and outputs.

·         The variables declared within the task are local to that task.

·         tasks can call another task or function.

·         tasks can be used for modeling both combinational and sequential logic.

·         A task must be specifically called with a statement, it cannot be used within an expression as a function can.

 module  task_calling (temp_a, temp_b, temp_c, temp_d);

 input [7:0] temp_a, temp_c;

 output [7:0] temp_b, temp_d;

 reg [7:0] temp_b, temp_d;

                 

  always @ (temp_a)

  begin  

    convert (temp_a, temp_b);

  end 

  always @ (temp_c)

  begin        

    convert (temp_c, temp_d);

  end 

task convert;

 begin

                 temp_out = (9/5) *( temp_in + 32);

 end

endtask

endmodule

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