IMAGE PROCESSING IN VERILOG - ADD IMAGES IN VERILOG - MATLAB XILINX MODELSIM

In previous postings, we have seen how to Convert an Image into Text file for processing in HDL (verilog, VHDL) Now let us see how to process the text converted image in Verilog. We have implemented this in Xilinx and Modelsim.

The flow is simple
1. Read the text file
2. Convert to hexadecimal/binary
3. Pass to adder
4. Get the sum/output
5. Write to text file.

After that using matlab function, convert the output text file back to image.

The verilog codes are as follows,,
MAIN MODULE:
module imaddr(rstb,clk,en,a,b,sum,car);
 input rstb,clk,en;
 input [7:0] a,b;
 output reg [7:0] sum;
 output reg car;
always @ (negedge clk or negedge rstb) begin
  if(rstb==0)
   begin sum=0; car=0; end
  else begin
       if(en==1)
          begin {car,sum}=(a+b); end //en if
    end //else end
end
endmodule


TEST BENCH:
File Read:
    $readmemh("y_out.txt", hexad);
The image pixel value is read into "hexad" variable & then it is converted to decimal for processing.


Passing pixel values to IMAdder
//store output value @negedge since UUT is NEGEDGE sensitive ie, UUT produces output @ NegEdge
always @ (negedge clk) begin
  if(rstb==1 && en==1 && w!=(n+1)) begin
        if(w!=n) begin //check if count reaches max (image size)
              a<=decim[w]; b<=decim2[w]; //put values for UUT
        out[w]=sum; //store UUT output to array
        $fwrite(outfile,"%d\n",sum);
        $display("\n%d",sum);
        w=w+1; //increment count
           end
        else begin a<=a; b<=b; end
    end
  else if(w==(n+1) && done==0) begin done=1;    $display("Img Adding complete..."); end


CLICK HERE TO DOWNLOAD:   IMADDER.v    TESTBENCH.v

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