Image Processing in VHDL - Adding Images VHDL code

      Often image processing in HDL (verilog/VHDL) is a bit complex task when it comes for simulation & implementation in real environment where the image has to be converted into a HDL compatible form.

     We have already seen how to convert an image into text and to reconstruct image back from a text file [ Click here to view it. ] and also how to process them in Verilog. Now let us see how to do it in VHDL.

        In previous postings, VHDL file read write operations & datatype conversions have been described.  

The steps involved in image processing in VHDL are

1. Image to text in Matlab
2. Read text in VHDL
3. Convert real value (read from text) into bit vector
4. Process the bit vector & get required result
5. Convert the resultin bit vector to integer (decimal)
6. Write to output text file
7. Reconstruct output image from output text file
   

      The code is organised into different processes such as Clock generator, read and write. The clock generator produces the clock signal for the TB & DUT.

      The reading process reads the text file, converts it to bit vector and assigns to the input ports of DUT i.e., Image Adder. Once the EOF of the input text file is reached, the endoffile signal is set indicating the task completion.

     The write process gets the result vector, converts it to integer & writes to text file until the endoffile signal is in state '0'.

Read Process:
                 if (not (endfile(infile) or endfile(infile2)) ) then --checking the "END OF FILE" is not reached.
                    readline(infile, inline);
                    read(inline, dataread1);
                    d1 <=integer(dataread1);
                a <= CONV_INT2STDLV(d1,8);
                    readline(infile2, inline2);
                    read(inline2, dataread1);
                    d2 <=integer(dataread1);
                b <= CONV_INT2STDLV(d2,8);
        else   
                a<=x"00";
                b<=x"00";
                endoffile <='1'; --set signal to tell end of file read file is reached.
        end if;

Write process:
         if(endoffile='0') then --if the file end is not reached.
            intt <= CONV_STDLV8bit_2INT(sum);
            if(linenumber>3) then
            write(buff_out, intt); 
            writeline(outfile, buff_out);-- write line to output_image text file.
            n <= n+1;
          end if;   
            linenumber <= linenumber + 1;
         end if;

The simulation output is....



Click here to download the VHDL files    IMADDER.vhd         TestBench.vhd

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