VHDL Real/interger to STD Logic Vector and STD Logic vector to Integer datatype conversion code example

     Here is a simple function for converting integer number to STD logic vector and vice versa. The width can be easily adjusted upto 32 bits (max size of integer number).

     This is very useful in handling file i/o for processing images into VHDL modules.

STD LOGIC VECTOR to 8 bit INTEGER:

function CONV_STDLV8bit_2INT(ARG: std_logic_vector (7 downto 0))
return integer is
variable int: integer:=0;
variable tmp: std_logic_vector(7 downto 0);
begin
    int :=0;
    tmp := ARG;
    for i in 0 to 7 loop
        if (tmp(i) ='1') then
            int := int+(2**i);
        else
            int := int+0;
        end if;
    end loop;
    return int;
end CONV_STDLV8bit_2INT;

INTEGER to 8 bit STD LOGIC VECTOR:

function CONV_INT2STDLV(ARG: INTEGER)
return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (7 downto 0):=x"00";
variable SIZE: integer:= 8;
variable temp: integer:= 0;
begin
    temp := ARG;
    for i in 0 to SIZE-1 loop
        if ((temp mod 2) = 1) then
            result(i) := '1';
        else
            result(i) := '0';
        end if;
        if temp > 0 then
            temp := temp / 2;
        elsif (temp > integer'low) then
            temp := (temp - 1) / 2; -- simulate ASR
        else
            temp := temp / 2; -- simulate ASR
        end if;
    end loop;
    return result;
end CONV_INT2STDLV;

Example for using the above functions
a is STD_L_V 7 to 0
           a <= CONV_INT2STDLV(din);

intt is integer variable
             intt <= CONV_STDLV8bit_2INT(sum);

 

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