VHDL ATTRIBUTES – USAGE – EXAMPLES

VHDL ATTRIBUTES – USAGE – EXAMPLES

            Here we introduce you to VHDL attributes which are predefined, its syntax, usage and its examples in this posting.

            The syntax of an attribute is some named entity followed by an apostrophe and one of the following attribute names. A parameter list is used with some attributes.

Definitions: TYPE represents any data type, ARRAY represents any array or constrained array type, SIGNAL represents any signal and  ENTITY represents a named entity.

SYNTAX	DESCRIPTION
TYPE'BASE	is the base type of the type TYPE
TYPE'LEFT	is the leftmost value of type TYPE. (Largest if downto)
TYPE'RIGHT	is the rightmost value of type TYPE. (Smallest if downto)
TYPE'HIGH	is the highest value of type TYPE.
TYPE'LOW	is the lowest value of type TYPE.
TYPE'ASCENDING	is boolean true if range of TYPE defined with to .
TYPE'IMAGE(X)	is a string representation of X that is of type TYPE.
TYPE'VALUE(X)	is a value of type TYPE converted from the string X.
TYPE'POS(X)	is the integer position of X in the discrete type TYPE.
TYPE'VAL(X)	is the value of discrete type TYPE at integer position X.
TYPE'SUCC(X)	is the value of discrete type TYPE that is the successor of X.
TYPE'PRED(X)	is the value of discrete type TYPE that is the predecessor of X.
TYPE'LEFTYPEOF(X)	is the value of discrete type TYPE that is left of X.
TYPE'RIGHTYPEOF(X)	is the value of discrete type TYPE that is right of X.
ARRAY'LEFT	is the leftmost subscript of array ARRAY or constrained array type.
ARRAY'RIGHT	is the rightmost subscript of array ARRAY or constrained array type.
ARRAY'HIGH	is the highest subscript of array ARRAY or constrained array type.
ARRAY'LOW	is the lowest subscript of array ARRAY or constrained array type.
ARRAY'RANGE	is the range  ARRAY'LEFT to ARRAY'RIGHT  or  ARRAY'LEFT downto ARRAY'RIGHT .
ARRAY'REVERSE_RANGE	is the range of ARRAY with to and downto reversed.
ARRAY'LENGTH	is the integer value of the number of elements in array ARRAY.
ARRAY'ASCENDING	is boolean true if range of ARRAY defined with to .
SIGNAL'DELAYED(t)	is the signal value of SIGNAL at time now - t .
SIGNAL'STABLE	is true if no event is occurring on signal SIGNAL.
SIGNAL'STABLE(t)	is true if no even has occurred on signal SIGNAL for t units of time.
SIGNAL'QUIET	is true if signal SIGNAL is quiet. (no event this simulation cycle)
SIGNAL'QUIET(t)	is true if signal SIGNAL has been quiet for t units of time.
SIGNAL'TRANSACTION	is a bit signal, the inverse of previous value each cycle SIGNAL is active.
SIGNAL'EVENT	is true if signal SIGNAL has had an event this simulation cycle.
SIGNAL'ACTIVE	is true if signal SIGNAL is active during current simulation cycle.
SIGNAL'LAST_EVENT	is the time since the last event on signal SIGNAL.
SIGNAL'LAST_ACTIVE	is the time since signal SIGNAL was last active.
SIGNAL'LAST_VALUE	is the previous value of signal SIGNAL.
SIGNAL'DRIVING	is false only if the current driver of SIGNAL is a null transaction.
SIGNAL'DRIVING_VALUE	is the current driving value of signal SIGNAL.
ENTITY'SIMPLE_NAME	is a string containing the name of entity ENTITY.
ENTITY'INSTANCE_NAME	is a string containing the design hierarchy including ENTITY.
ENTITY'PATH_NAME	is a string containing the design hierarchy of ENTITY to design root.

Examples and its outcome of the Attributes are as follows...

type RAMtype is array ( 0 to 4) of std_logic_vector(11 downto 0);   type ROMtype is array ( 5 downto 1) of std_logic_vector(11 downto 0);   signal ram : RAMtype := (x"123", x"50C", x"874", x"651", x"ab4");   constant rom : ROMtype := (x"000", x"329", x"B7E", x"05C", x"0F9");  type mlv7 is ('0','1','X','Z','H','L','W');  subtype mlv4 is mlv7 range '0' to 'Z';  subtype mlv2 is mlv7 range '0' to '1';  signal i:integer;

STATEMENT	RESULT
report "mlv7'image(mlv4'base'high): " & mlv7'image(mlv4'base'high);	mlv7'image(mlv4'base'high): 'W'
report "mlv4'image(mlv2'base'low): "  & mlv4'image(mlv2'base'low);	mlv4'image(mlv2'base'low): '0'
report "mlv7'image(mlv2'base'low): "  & mlv7'image(mlv2'base'low);	mlv7'image(mlv2'base'low): '0'
report "mlv4'image(mlv2'base'low): "  & mlv4'image(mlv2'base'low);	mlv4'image(mlv2'base'low): '0'
report "RAMtype'left : " & integer'image(RAMtype'left);	RAMtype'left : 0
report "RAMtype'right: " & integer'image(RAMtype'right);	RAMtype'right: 4
report "RAMtype'high : " & integer'image(RAMtype'high);	RAMtype'high : 4
report "RAMtype'low  : " & integer'image(RAMtype'low);	RAMtype'low  : 0
report "ROMtype'left : " & integer'image(ROMtype'left);	ROMtype'left : 5
report "ROMtype'right: " & integer'image(ROMtype'right);	ROMtype'right: 1
report "ROMtype'high : " & integer'image(ROMtype'high);	ROMtype'high : 5
report "ROMtype'low  : " & integer'image(ROMtype'low);	ROMtype'low  : 1
report "RAMtype'ASCENDING: " & boolean'image(RAMtype'ASCENDING);	RAMtype'ASCENDING: true
report "ROMtype'ASCENDING: " & boolean'image(ROMtype'ASCENDING);	ROMtype'ASCENDING: false
report "boolean'value(true) : " & boolean'image(boolean'value("true"));	boolean'value(true) : true
report "boolean'value(false): " & boolean'image(boolean'value("false"));	boolean'value(false): false
report "std_logic'value(0): " & std_logic'image(std_logic'value("0"));	std_logic'value(0): '0'
report "std_logic'value(1): " & std_logic'image(std_logic'value("1"));	std_logic'value(1): '1'
report "mlv7'pos('X'): "  & integer'image(mlv7'pos('X'));	mlv7'pos('X'): 2
report "mlv7'val(4)  : "  & mlv7'image(mlv7'val(4));	mlv7'val(4)  : 'H'
report "mlv7'succ('X'): " & mlv7'image(mlv7'succ('X'));	mlv7'succ('X'): 'Z'
report "mlv7'pred('X'): " & mlv7'image(mlv7'pred('X'));	mlv7'pred('X'): '1'
report "mlv7'leftof('L') : " & mlv7'image(mlv7'leftof('L'));	mlv7'leftof('L') : 'H'
report "mlv7'rightof('L'): " & mlv7'image(mlv7'rightof('L'));	mlv7'rightof('L'): 'W'
report "ram'left : " & integer'image(ram'left);	ram'left : 0
report "ram'right: " & integer'image(ram'right);	ram'right: 4
report "ram'high : " & integer'image(ram'high);	ram'high : 4
report "ram'low  : " & integer'image(ram'low);	ram'low  : 0
report "rom'left : " & integer'image(rom'left);	rom'right: 1
report "rom'right: " & integer'image(rom'right);	rom'high : 5
report "rom'high : " & integer'image(rom'high);	rom'low  : 1
report "rom'low  : " & integer'image(rom'low);
report "rom'length  : " & integer'image(rom'length);	rom'length  : 5
report "ram'length  : " & integer'image(ram'length);	ram'length  : 5
report "rom'range"; for i in rom'range loop report "i= " & integer'image(i); end loop;	rom'range  i= 5  i= 4  i= 3  i= 2  i= 1
report "ram'range"; for i in ram'range loop report "i= " & integer'image(i); end loop;	ram'range  i= 0  i= 1  i= 2  i= 3  i= 4
report "ram'reverse_range"; for i in ram'reverse_range loop report "i= " & integer'image(i); end loop;	ram'reverse_range  i= 4  i= 3  i= 2  i= 1  i= 0
REPORT "ttttt'SIMPLE_NAME: " & ttttt'SIMPLE_NAME; REPORT "ttttt'INSTANCE_NAME: " & ttttt'INSTANCE_NAME; REPORT "ttttt'PATH_NAME: " & ttttt'PATH_NAME; *where "ttttt" is an single entity without hierarchy. Simulation is performed on "ttttt" alone. *Note that this only if the entity has hierarchial instance.	ttttt'SIMPLE_NAME: ttttt ttttt'INSTANCE_NAME: :ttttt(stim): ttttt'PATH_NAME: :ttttt:

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